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sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 1 d escription the sc1405c d ual high speed mosfet driver pr o- vides a complete solution to driving mosfets in sy n- chronous converters. the sc1405c features internal overlap protection to ensure that low - side fet does not turn on until the hi gh - side fet has turned off. each gate output drives a 3000pf load in 15ns rise/fall time and has ultra fast propagation delay to the gate of the power fet?s. the delay between the low - side gate going low to the high - side gate switching high is externally p rogrammable via a capacitor for optimal reduction of switching losses at the desired operating frequency. the low - side fet may b e disabled at light loads by keeping mod e low to trigger asynchronous operation, thus saving it?s gate drive current and inductor ripple current. the sc1405c provides overvoltage protection independent of the pwm feedback loop with a unique ?adapti ve ovp? compar a tor which rejects noise but responds quickly to a real ovp situation. under - voltage lock - out circuitry guarantee s both driver outputs are low when the 5v power supply is less than or equal to 4.4v (typ) at supply ramp up (4.35v at supply ram p down). a cmos output indicates the status of the 5v supply. a logic low on the enable input places the ic in stand - by mode red ucing supply current to less than 10a. sc1405c is offered in a tssop package. features fast rise and fall times (15ns with 3000pf load) 14ns max. p ropagation delay (bg going low) adaptive/programmable shoo t - through protection wide input voltage range (4.5 - 25v) programmable delay between mosfet?s power saving asynchronous mode contr ol adaptive overvoltage protection internal thermal shutdown under - voltage lock - out less than 10a stand - by current (en=low) pow er ready output signal high frequency (to 1.2mhz) operation allows use of small inductors and low cost capacitors applica tions high d ensity , f ast response power supplies motor drives/class - d amps portable computers tel:805 - 498 - 2111 fax:805 - 498 - 3804 web:http://www.semtech.com device (1) package temp. range (t j ) sc1405c ts tssop - 14 0 - 125c ordering information note: (1) add suffix ?tr? for tape and reel. conceptual application circuit sc1406g imvp controller sc1406g imvp controller vid [4:0] vid [4:0] sc1405 smart mosfet driver sc1405 smart mosfet driver lo +vcc_cpu_core +vcc_cpu_core co 3.3v +vcc_cpu_io +vcc_cpu_io +vcc_cpu_clk +vcc_cpu_clk 1.5v 2.5a 2.5v 150ma +v_in +v_5 3.3v 0.925v - 2.0v up to 14a ldo controller ldo controller pwm controller sc1406g imvp controller sc1406g imvp controller vid [4:0] vid [4:0] sc1405 smart mosfet driver sc1405 smart mosfet driver lo +vcc_cpu_core +vcc_cpu_core co 3.3v +vcc_cpu_io +vcc_cpu_io +vcc_cpu_clk +vcc_cpu_clk 1.5v 2.5a 2.5v 150ma +v_in +v_5 3.3v 0.925v - 2.0v up to 14a ldo controller ldo controller pwm controller
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 2 note: (1) specification refers to application circuit in figure 1. absolute maximum ratings parameter maximum units v cc supply voltage - 0.3 to 7 v bst to pgnd - 0.3 to 30 v bst to drn (steady - state) - 0.3 to 7 v bst to drn (transient, < 100ns) - 0.3 to 8 v drn to pgnd - 2 to 25 v ovp to pgnd - 0.3 to 10 v en, co, dsps, mode, prdy, delay, to agnd - 0.3 to 7.3 v agnd to pgnd - 1 to 1 v electrical characteristics (dc operating specifications) unless specified: - 0 < q j < 125c; v cc = 5v; 4v < v bst < 26v parameter symbol conditions min typ max units power supply supply voltage vcc 4.15 5 6.0 v quiescent current iq en = 0v 10 a quiescent current, operating iq v cc = 5v,co=0v 1 m a prdy high level output voltage v cc = 4.6v, lload = 10ma 4.5 4.55 v low level output voltage v cc < uvlo threshold, lload = 10a 0.1 0.2 v dsps_dr high level output voltage v cc = 4.6v, cload = 100pf 4.15 v low level output voltage v cc = 4.6v, cload = 100pf 0.05 v under - voltage lockout start threshold 4.2 4.4 4.6 v hysteresis vhys 0.05 v logic active threshold 1.5 v en is low parameter symbol conditions max imum units continuous power dissipation pd tamb = 25 c , t j = 125 c 0.66 w thermal resistance junction to case q jc 40 40 c/w thermal resistance junction to ambient q ja 150 150 c/w operating junction temperature range t j 0 to +125 0 to +125 c storage temperature range t stg - 65 to +150 - 65 to +150 c l ead temperature (soldering) 10 sec t lead 300 300 c thermal ratings
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 3 electrical characteristics (dc operating specifications) cont. parameter symbol conditions min typ max units overvoltage protection trip threshold 1.145 1.2 1.255 v hysteresis 0.8 v trip delay, 50mv overdrive t = 0 to 125oc 300 470 800 ns trip delay , 100mv overdrive t = 0 to 125oc 1 25 2 25 40 0 ns s_mod high level input voltage 2.0 v low level input voltage 0.8 v enable high level input voltage 2.0 v low level input voltage 0.8 v co high level input voltage 2.0 v low level input voltage 0.8 v thermal shutdown over temperature trip point 165 c hysteresis 10 c high - side driver peak output current 2 a output resistance duty cycle < 2%, tpw < 100s, t j = 125c, v bst - v drn = 4.5v, v tg = 4.0v source +v drn or v tg = 0.5v (sink)+v drn 1 .7 w w low - side driver peak output current 2 a output resistance 1.2 1.0 w w duty cycle < 2%, tpw < 100s, t j = 125c vcc = 4.6v, v bg = 4v source , or vbg = 0.5v (sink)
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 4 electrical characteristics (dc operating specifications) cont. parameter symbo conditions min typ max units ac operating specifications high - side driver ( see fig. 2) r ise time tr tg , ci = 3nf, v bst - v drn = 4.6v, 14 23 ns f all time tf tg ci = 3nf, v bst - v drn = 4.6v, 12 19 ns p ropagation delay time, tg going high tpdh tg ci = 3nf, v bst - v drn = 4.6v, c - delay=0 20 32 ns p ropagation delay time, tg going low tpdl tg ci = 3nf, v bst - v drn = 4.6v, 15 24 ns low - side driver ( see fig. 2) r ise time tr bg ci = 3nf, v v_5 = 4.6v, 15 24 ns f all time tr bg ci = 3nf, v v_5 = 4.6v, 13 21 ns p ropagation delay time tpdh bghi ci = 3nf, v v_5 = 4.6v, 12 19 ns p rogagation delay time tpdl bg ci = 3nf, v v_5 = 4.6v, 7 12 ns under - voltage lockout v cc ramping up propogation delay tpdh uvlo en is high 10 us v cc ramping down delay tpdl uvlo en is high 10 us pr opogation d ela y en is transitioning from low to high v cc > uvlo threshold, delay measured from en > 2.0v to prdy 10 s en is transitioning from high to low v cc > uvlo threshold. delay measured from en < 0.8v tp prdy 500 s dsps_dr r ise/fall time ci = 100pf, vcc = 4.6v, 20 ns p ropagation delay, s_mod goes high and 10 ns p ropagation delay s_mod goes high and bg goes low 10 ns overvoltage protection p ropagation delay ovp_s going high 1 s v cc = 4.6v, t j = 125c, ovp_s > 1.2v to bg > 90% of v cc
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 5 block diagram
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 6 note: (1) all logic level inputs and outputs are open collector ttl compatible. pin # pin name pin function 1 ovp overvoltage protection sense. external scaling resistors required to set 2 en when high, this pin enables the internal circuitry of the device. when low, tg, bg and prdy are forced low and the supply curren t ( vcc ) is 3 gnd logic gnd. 4 co ttl - level input signal to the mosfet drivers. 5 mod e when low, this signal forces bg to be low. when high, bg is the inverse of co. 6 delay sets the additional propagation delay for bg going low to tg going 7 prdy this pin indicates the status of 5v. when 5v is less than 4.4v(typ) this output is driven low. when 5v is greater than or equals to 4.4v(typ) this output is driven to 5v level. this output has a 10ma drive capability and 8 v cc +5v supply. a .22 - 1f ceramic capacitor should be connected from 5v 9 bg output drive for the synchronous (low - side) mosfet. 10 pgnd power ground. connect to the synchronous fet power ground. 11 dspout dynamic set point switch drive. ttl level output signal. when s_mod 12 drn this pin connects to the junction of the switching and synchronous mosfet?s. this pin can be subjected to a - 2v minimum relative to 13 tg output gate drive for the switching (high - side) mosfet. 14 bst bootstrap pin. a capacitor is connected between bst and drn pins to develop the floating bootstrap voltage for the high - side mos fet. the pin description pin configuration top view (14 - pin tssop)
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 7 typical distributed power supply application circuit figure 1. dsps_dr p_ready pwm in +5v input power + 10uf,6.3v + + + + + + 2.2 2.2 .22uf 47pf .1uf mtb75n03 mtb75n03 d1 1n5819 sc1405 13 4 3 2 1 14 6 5 10 7 9 11 12 8 tg co gnd en ovp_s bst delay_c s_mod pgnd prdy bg dsps_dr drn vcc (20khz-1mhz) << << >> 75a,30v 75a,30v <<< output feedback to pwm controller over-voltage sense timing diagram figure 2.
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 8 figure 3 - application evaluation board schematic figure 3 r19 0/0805 c20 150uf/4v +5vcc c13 1nf dac ovps c25 150u/4v c26 1uf/0805 vcc_1406 c5 100pf q1 mmbt4403 3 1 2 c4 1uf/0805 d q3 irf7811a 4 1 2 3 5 6 7 8 core clref r8 20k offset delayc bg1 vid2 c9 1nf d q5 irf7809a 4 1 2 3 5 6 7 8 base15 r5 1.00k c23 no-pop vid1 v_gate phase r17 27/1206 c21 150uf/4v d2 mbrs340 1 2 r18 10 r21 1.30k c29 10uf/1206 vid0 r14 10.0k vid1 c16 1uf/0805 c22 150uf/4v c1 4.7uf/50v +3.3v +v_in c10 1.8nf c3 4.7uf/50v c11 1.2nf u2 sc1405c 1 2 3 4 5 6 7 14 8 9 10 11 12 13 ovps en gnd co smod delayc prdy bst vcc bg pgnd dspsdr drn tg c15 47pf vid4 r22 100k r12 0 1 2 3 4 r23 lrf3w_003_5% bst r3 1.00k c14 270pf c24 no-pop cl cmpref c31 1pf cs c17 0.22uf/0805 c19 150uf/4v vid2 r1 196k l_r l1 1.5uh r6 1.00k hys c6 56pf cmp bg2 r9 43k tg1 c18 1nf/0805 cs- c12 1nf en bg bal 2_5v sslr d1 mbr0530 1 2 hys u1 sc1406g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 hys clset vcout vcin vcbyp vid4 vid3 vid2 vid1 vid0 base25 fb25 base15 fb15 en pwrgd lbin sslr sscore core dac gnd co vcc cmp cmpref cl clref d q4 irf7809a 4 1 2 3 5 6 7 8 c2 4.7uf/50v vid0 c28 1uf/50v/1206 cs+ +vcccpu_core r2 86.6k dac r11 0 lbin sscore clset r4 1.00k en base25 r15 6.65k c8 0.22uf/0805 clset 1_5v vid4 q2 mjd45h11 1 4 3 vid3 co cloh c27 150uf/4v c7 56pf r13 1 oh gnd tg vid3
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 9 a pplication informati on: sc1405 c is the newest high speed driver in the sc1405 family . it drive s l ow r ds_on power mosfets with rapid rise/fall times and propagation delays. as pwm con verter frequency i ncreases to reduce power stage volume and cost, fast rise and fall times are necessary to minimize switching losses of the high - side fet and reduce d ead - time of the low - side fet. while l ow r ds_on mosfets have lower conduction ( i 2 r ) losses, t heir die area is larger and the input capacitance of the fet is h igher . faster drivers are required to reduce the resulting switching losses. often a 50% decrease in r ds_on more than doubles the r e quired input gate charge supplied by the driver. the r ds_on power savings can be offset by the switching and dead - time l osses with a sub - optimum driver. while discrete solution s can achieve reasonable drive capability, implementing shoot - through, programmable delay and other housekeeping functions necessary for high reliability is cumbersome and costly. the sc14 05 family of parts presents a total solution for the high - speed, high power density applications. the w ide input supply range o f 4.5v - 25v allows use in battery powered applications, new high voltage, distributed power servers as well as class - d amplifiers . theory of operation the control input (co) to the sc1405 c is typically supplied by a pwm controller that regulates the power supply output. (see application evaluation schematic, figure 3). the timing diagram demonstrates the sequence of events by wh ich the top and bottom drive signals are applied. the shoot - through protection is implemented by holding the bottom fet off unt il the voltage at the phase node (intersection of top fet source, the output inductor and the bottom fet drain) has dropped belo w 1v. this assures that the top fet has turned off and that a direct current path does not exist between the input supply and g round, a condition which both the top and bottom fets are on momentarily. the top fet is also prevented from turning on until t he bottom fet is off. this time is internally set to 20ns (typical) and may be increased by adding a capacitor to the delay pin. the add i- tional delay is approximately 1ns/pf . the external capacitor is recommended when multiple low r ds_on mosfets are used in paral lel and the fall time is greater than 20ns. please note that excessive values of d elay capacitor reduce s efficiency since the p arallel s c hottky or the bottom fet body diode conduct s during dead - time. layout guidelines as with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the sc1405 c . the e valuation board schematic (refer to figure 3) shows a mobile cpu synchronous design with all surface mountable components. while the placement and wiring of components connecting to delay , en, mod e , dsps and prdy are not critical, tight placement and short, wide traces must be used in layout of tg, bg , drn, ovp, and especially the pgnd pin. the top gate driver supply voltage is provided by bootstrapping the +5v supply and adding it the phase node voltage (drn). since the bootstrap capacitor supplies the charge to the top gate driver , it must be less than .5? away from the sc1405. ceramic x7r capacitors are a good choice for supply bypassing near the chip. the vcc cap acitor must also be less than .5? away from the sc1405. the ground node of this capacitor, the sc1405 pgnd pin and the s ource o f the low - side fet must be very close to each other, preferably with common pcb copper land and multiple vias to the ground plan e (if used). the parallel s c hottky must be physically next to the low - side fet d rain and source. any trace or lead inductance in these connections deflects current from the s c hottky and allow s it to flow through the fet?s b ody diode, thus reducing effic iency. preventing inadverte nt bottom fet turn - on especially a t high input voltages, (12v and greater) rapid turn - on of the high - side fet creates a positive going spike on the low - side fet?s gate through the miller capacitance, crss of the low - side fe t. the voltage appearing on the gate due to this spike is: vspike=vin* c rss/(crass+ c iss) in this equation, ciss is the input g ate capacitance of the low - side fet , and assum es the impedance of the drive path is high compared to the instantaneous impedance of the capacitors , since dv/dt and thus the effective frequency is very high. if the bg pin of the sc1405 c is very c lose to the low - side fet, vspike is reduced , depending on trace inductance and the var i- ables in the above equation. while not shown in figure 3, a capacitor may be
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 10 added from the gate of the low - side fet to its source, preferably less than .1? away. this capacitor increases ciss in the abo ve equation to reduce the effective spike voltage, vspike. pay attention to the crss/ciss ratio when selecting the low - side fet . a low ratio reduces the miller feedback and thus reduces vspike. also , mosfets with higher threshold voltages conduct at a higher voltage and will not turn on during the spike. a zero ohm bg gate resistor help keep the gate voltage low. ultimately, slowing down the top fet by adding gate resistance will reduce d v /dt which will in turn make the effective impedance of the capa citors higher, thus allowing the bg driver to hold the bottom gate voltage low. ringing on the phase node the high - side mosfet source must be close to the bottom mosfet drain to reduce parasitic leakage i n- ductances which drive the phase node negative , and produces the ringing on the phase node . this frequency is determined by: f r ing =1/(2 ? * sqrt(l st *coss)) , w here: l st is the effective stray inductance of the high - side fet plus t he trace inductance o f the connection between the fet , plus the inductance of the low - side fet , plus to the inter connection inductance through the ne arest high frequency decoupling capacitor . coss = drain to source capacitance of bottom fet. if there is a schottky used, the capacitance of the scho t- tky is added to the value. although this ringing does not pose significant power losses due to a fairly high q, it may cause t he phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. this ringing i s also an emi nuisance due to its high resonant frequency. adding a capacitor, typically 1000 - 2000pf, in parallel with coss can often eliminate the emi issue. if double pulsing is caused due to excessive ringing, placing 4.7 - 10 ohm resistor between the ph ase node and the drn pin of the sc1405 is recommended to cure the problem . proper layout minimizes ringing , and so the need fo r external components. use of so - 8 or other surface mount mosfets reduce s lead inductance and their parasitic effects. asynchr onous operation the sc1405 c can be configured to operate in a sy n- chronous mode by pulling mode to logic low, thus disabling the low - side fet drive. this can sav e power at light loads since the low - side fet?s gate capacitance does not have to charged at the switching frequency. another efficiency benefit to operating i n asynchronous mode is preventing reverse current flow . when operating in synchronous mode, the inductor current can go negativ e and flow in reverse direction when the bottom fet is on and the dc load is less than 1/2 inductor ripple current. at that poi nt, the inductor core and wire losses, depending on the magnitude of the ripple current, can be significant. operating in async hronous mode at light loads effectively only charges the inductor by as much as needed to supply the load current, since the ind uctor never completely discharges at light loads. dc regulation can be an issue depending on the type of controller used and mi nimum load required to maintain regulation. if there are no schottky s used in parallel with bottom fet, the fet?s body diode wi ll conduct in asynchronous mode. the high voltage drop of this diode must be considered when determining the criteria for this mode of operation. dsps dsps is a logical duplicate of the bottom fet?s gate drive, if mod e is held low. ovp / over temp eratu re shutdown output over - voltage protection (ovp) may be implemented on the sc1405 independent of the pwm controller . a voltag e divider from the output is compared with the internal bandgap voltage of 1.2v (typical). upon exceeding this voltage, the over voltage comparator disables the top fet, while turning on the bottom fet to discharge the output capacitors through the output i nductor. the sc1405c has a unique adaptive ovp circuit. short noise pulses, less than ~100ns are rejected co m pletely; longer pulses will trigger ovp if only of su f ficient magnitude. a long term transient will trigger ovp with a smaller magnitude. provide a single switching period rc time constant a nd at least 250mv headroom on the ovp pin to pr e- vent false ovp events . the sc1405 will shutdown if its tj exceeds 165c.
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 11 figure 4 - timing diagram: ch1:co input ch2:tg drive ch3:bg non - overlap drive ch4:phase node iout=20a (10a/phase) refer to eva l. schematic (fig.3) figure 5 - timing diagram: rise/fall times ch1:tg drive ch2:bg drive cursor:tpdh tg iout=20a (10a/phase) refer to eval. schemat ic (fig. 3) performance diagrams, application evaluation board. (fig. 4 ) vin = 12v,vout = 1.6v top fet=ir7811 fdb7030(bl) qgd = 23nc
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 12 sc1405c ovp delay vs. temperature 0.00 100.00 200.00 300.00 400.00 500.00 600.00 -25 -5 15 35 55 75 95 115 135 temperature (c) delay (ns) 50mv overdrive 100mv overdrive figure 6 - delay vs. temp typical delay vs. overdrive (t=25c) 100 1000 10000 10 1000 overdrive (mv) delay (ns) figure 7 - delay vs. overdrive
sc1405c high speed synchronous power mosfet smart driver ? 2000 semtech corp. 652 mitchell road newbury park ca 91320 preliminary 13 outline drawing tssop - 14 ecn00 - 924

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